PPT ON MICROPROCESSOR AND IT'S ARCHITECTURE

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Microprocessor And it's Architecture Presentation Transcript:
1.The Microprocessor and its Architecture

2.Intel Architecture

3.Programming Model

4.General-Purpose Registers
The top portion of the programming model contains the general purpose registers: EAX, EBX, ECX, EDX, EBP, ESI, and EDI.  
These registers, although general in nature, each have special purposes and names.
EAX – Accumulator (as general as they come) used also as AX, AH, and AL
EBX – Base Index often used to address memory data (BX, BH, and BL)

5.ECX – count used in shifts and loops (CX, CH, and CL)
EDX – data used in multiply and divide (DX, DH, and DL)
EBP – base point used to address stack data (BP)
ESI – source index addresses memory data (SI)
EDI – destination index addresses memory data (DI)

6.Special-Purpose Registers
The special purpose register each have specific tasks and are ESP, EIP, and EFLAGS
ESP – address stack data used in functions (procedures) and temporary storage (SP)
EIP – addresses the next instruction in a program (IP)
EFLAGS – indicates conditions of the microprocessor (FLAGS) 

7.FLAGS

8.The Flags
C – holds a carry or a borrow 
P – the parity flag (little use today)
A – auxiliary flag used with DAA and DAS
Z – zero 
S – sign 
O – Overflow 
D – direction (used with string instructions)
I – interrupt (interrupt on/off)
T – trap flag (trace on/off)

9.Newer Flag Bits
IOPL – I/O privilege level for Windows 
NT – nested task
RF – resume flag
VM – virtual mode
AC – alignment check
VIF – virtual interrupt (copy of interrupt flag)
VIP – virtual interrupt pending
ID = CPUID instruction available

10.Segment Register   
The segment registers are: CS (code), DS (data), ES (extra), SS (stack), FS, and GS.
Segment registers address a section of memory in a program.  A segment is either 64K in length (real mode) or up to 4G in length (protected mode).
All code (programs) reside in the code segment.

11.Default Segments for Offset address

12.Real Mode Memory Addressing
Real mode memory is the first 1M of the memory system.
All real mode addresses are a combination of a segment address plus an offset address.
The segment address (16-bits) is appended with a 0H or 00002 to form a 20-bit address.  (or multiplied by 10H)
The effective address is this 20-bit segment address plus a 16-bit offset address.

13.Defaults
Default 16-bit addresses are programs in CS, stack data in SS, and most other data in a program in DS.
Default 32-bit addresses are programs in CS, stack data in SS and most other data in DS.
What’s the difference?  16-bit addresses use offset addresses in BX, SI, DI, BP, or an offset numeric value.  32-bit addresses use offset addresses in EAX, EBX, ECX, EDX, EBP, EDI, ESI or a numeric value.
Programs resides in segment CS addressed by IP/EIP
Stack data resides segment SS addressed by SP/ESP

14.Effective Address Calculations
EA = segment x 10H plus offset
        (a)   10023 = 10000 + 0023
        (b)    ABC34 = AAF00 + 0134
        (c)    21FF0 = 12000 + FFF0 
Example (a) contained 1000 in the segment register, example (b) contained a AAF0 in the segment register, and example (c) contained a 1200 in the segment register.   

15.Relocation
Segment and offset addressing allows for easy and efficient relocation of code and data.
To relocate code or data only the segment number needs to be changed.  For example, if an instruction appears at offset address 0002 the segment address does not matter because if it changes so does the effective address of he instruction.

Source: Power Point Presentations

PPT ON INTRODUCTION TO MICROPROCESSOR AND COMPUTER

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Introduction to Microprocessor and Computer Presentation Transcript: 
1.Introduction to Microprocessor and Computer

2.Mechanical Computing
The abacus circa 500 B.C. – the first calculator
Blaise Pascal – the first modern mechanical adder
Charles Babbage – the first true computer
50,000 machine parts
Herman Hollerith – the punched card system and founder of IBM

3.Early electronic computersKonrad Zuse – Z3 (relay logic at 5.33 Hz)
Alan Turing – Colossus
Fixed program computer
University of Pennsylvania – ENIAC
Could be reprogrammed by rewiring the circuit and could several man hours
17,000 vacuum tubes, 500 miles of wires
100K operations per second 

4.Early milestones
1948 – the transistor at Bell Labs
1958 – the integrated circuit
1961 – RTL digital logic (resistor-to-Transistor Logic)
1971 – the microprocessor (4004)

5.Early programming
Countess of Lovelace (1823) wrote programs for the Analytical Engine
Machine Language then Assembly Language
Grace Hopper (1957) develops FLOW-MATIC
FORTRAN by IBM, ALGOL, and RPG
COBOL –first wide spread language
BASIC and PASCAL as teaching languages

6.Modern programming
Visual BASIC (most common business)
Visual C/C++ (most common technical)
JAVA (most common web)
ADA  (used by DoD
PASCAL -control programs
C# (gaining on web)

7.Early Microprocessors
4004 the first microprocessor (4-bit) 16K RAM
50 KIPS
4040 improved speed
TMS-100 
8008 (8-bit)
Fairchild, MOS tech., Motorola, National semiconductor, Rockwell, Zilog
8080 (8-bit) 64K RAM, 2Mhz clock
8086 (16-bit) 1M RAM, 5MHz clock
80286 (16-bit) 16M RAM, 16MHz clock

8.32-bit Microprocessors
80386, 4G RAM, 33 MHz clock
80486, 4G RAM, 66 MHz clock
Pentium, 4G RAM, 66 MHz clock
Pentium Pro, 64G RAM, 133 MHz clock
Pentium II, 64G RAM, 233 MHz clock
Pentium III, 64G RAM, 500 MHz clock
Pentium 4, 64G RAM, 1.5 GHz clock

9.The P nomenclature
P1 – 8086/8088 class 
P2 – 80286 class 
P3 – 80386 class 
P4 – 80486 class 
P5 – Pentium class
P6 – Pentium Pro/Pentium II, Pentium III, and Pentium 4 class

10.Cache Memory
A temporary high speed memory that buffers the slower DRAM from the higher speed microprocessor.
Usages in bursts of 4 memory-sized chunks of data (today 4, 64-bit numbers)
Level 1 (small cache for local high-speed storage)
Level 2 (larger cache for local high-speed storage.
Level 3 (large cache on Pentium 4 chip)

11.High End Computers
Processor: Intel Pentium 4
Frequency: 3.2GHz
Power consumption: 103 W max.*
Process: 90nm

12.Lower Scale of Computers
Processor can consume no more
 than 250-300mW

13.Speed of Evolution
Processor
2X in speed every 1.5 years; 100X performance in last decade
Memory
DRAM capacity: 2X / 2 years; 64X size in last decade
Cost per bit:  improves about 25% per year
Disk
capacity: > 2X in size every 1.0 years
Cost per bit:  improves about 100% per year
250X size in last decade

14.Memory Organization    
Memory is organized in byte-sized (wide) chunks of data
Memory is numbered in bytes
Memory is number in hexadecimal addresses or locations
Modern memory is 64-bits wide containing 8 bytes per memory physical location.
Modern DRAM is SLOW! (40 ns per a random access)
Buffering and double clock edge transfers can speed memory access times to about 25 MHz

15.Microprocessor Internals

Source: Power Point Presentations